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[libvpx] Update to v1.12.0

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This commit is contained in:
Andrey Volk committed 2026-07-10 19:38:46 +03:00
1 parent 287a71dc66
commit b5046d2a76
572 files changed
+52900 -29493
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libs/libvpx/vpx_dsp/mips/macros_msa.h
+8 -8
View File
@@ -88,10 +88,10 @@
const uint8_t *psrc_lw_m = (const uint8_t *)(psrc); \
uint32_t val_lw_m; \
\
__asm__ __volatile__("ulw %[val_lw_m], %[psrc_lw_m] \n\t" \
\
: [val_lw_m] "=r"(val_lw_m) \
: [psrc_lw_m] "m"(*psrc_lw_m)); \
__asm__ __volatile__("lwr %[val_lw_m], 0(%[psrc_lw_m]) \n\t" \
"lwl %[val_lw_m], 3(%[psrc_lw_m]) \n\t" \
: [val_lw_m] "=&r"(val_lw_m) \
: [psrc_lw_m] "r"(psrc_lw_m)); \
\
val_lw_m; \
})
@@ -102,10 +102,10 @@
const uint8_t *psrc_ld_m = (const uint8_t *)(psrc); \
uint64_t val_ld_m = 0; \
\
__asm__ __volatile__("uld %[val_ld_m], %[psrc_ld_m] \n\t" \
\
: [val_ld_m] "=r"(val_ld_m) \
: [psrc_ld_m] "m"(*psrc_ld_m)); \
__asm__ __volatile__("ldr %[val_ld_m], 0(%[psrc_ld_m]) \n\t" \
"ldl %[val_ld_m], 7(%[psrc_ld_m]) \n\t" \
: [val_ld_m] "=&r"(val_ld_m) \
: [psrc_ld_m] "r"(psrc_ld_m)); \
\
val_ld_m; \
})
libs/libvpx/vpx_dsp/mips/sad_mmi.c
+40 -38
View File
@@ -334,19 +334,6 @@
"paddw %[ftmp3], %[ftmp3], %[ftmp1] \n\t"
#endif /* _MIPS_SIM == _ABIO32 */
// depending on call sites, pass **ref_array to avoid & in subsequent call and
// de-dup with 4D below.
#define sadMxNxK_mmi(m, n, k) \
void vpx_sad##m##x##n##x##k##_mmi(const uint8_t *src, int src_stride, \
const uint8_t *ref_array, int ref_stride, \
uint32_t *sad_array) { \
int i; \
for (i = 0; i < (k); ++i) \
sad_array[i] = \
vpx_sad##m##x##n##_mmi(src, src_stride, &ref_array[i], ref_stride); \
}
// This appears to be equivalent to the above when k == 4 and refs is const
#define sadMxNx4D_mmi(m, n) \
void vpx_sad##m##x##n##x4d_mmi(const uint8_t *src, int src_stride, \
const uint8_t *const ref_array[], \
@@ -364,8 +351,9 @@ static inline unsigned int vpx_sad64x(const uint8_t *src, int src_stride,
double ftmp1, ftmp2, ftmp3, ftmp4, ftmp5;
mips_reg l_counter = counter;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"pxor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"1: \n\t"
// Include two loop body, to reduce loop time.
SAD_SRC_REF_ABS_SUB_64
@@ -383,6 +371,7 @@ static inline unsigned int vpx_sad64x(const uint8_t *src, int src_stride,
: [src_stride]"r"((mips_reg)src_stride),
[ref_stride]"r"((mips_reg)ref_stride)
);
/* clang-format on */
return sad;
}
@@ -405,9 +394,11 @@ static inline unsigned int vpx_sad_avg64x(const uint8_t *src, int src_stride,
unsigned int sad;
double ftmp1, ftmp2, ftmp3, ftmp4, ftmp5;
mips_reg l_counter = counter;
mips_reg l_second_pred = (mips_reg)second_pred;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"pxor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"1: \n\t"
// Include two loop body, to reduce loop time.
SAD_SRC_AVGREF_ABS_SUB_64
@@ -424,11 +415,12 @@ static inline unsigned int vpx_sad_avg64x(const uint8_t *src, int src_stride,
: [ftmp1]"=&f"(ftmp1), [ftmp2]"=&f"(ftmp2), [ftmp3]"=&f"(ftmp3),
[ftmp4]"=&f"(ftmp4), [ftmp5]"=&f"(ftmp5), [counter]"+&r"(l_counter),
[src]"+&r"(src), [ref]"+&r"(ref),
[second_pred]"+&r"((mips_reg)second_pred),
[second_pred]"+&r"(l_second_pred),
[sad]"=&r"(sad)
: [src_stride]"r"((mips_reg)src_stride),
[ref_stride]"r"((mips_reg)ref_stride)
);
/* clang-format on */
return sad;
}
@@ -450,8 +442,9 @@ static inline unsigned int vpx_sad32x(const uint8_t *src, int src_stride,
double ftmp1, ftmp2, ftmp3, ftmp4, ftmp5;
mips_reg l_counter = counter;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"pxor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"1: \n\t"
// Include two loop body, to reduce loop time.
SAD_SRC_REF_ABS_SUB_32
@@ -469,6 +462,7 @@ static inline unsigned int vpx_sad32x(const uint8_t *src, int src_stride,
: [src_stride]"r"((mips_reg)src_stride),
[ref_stride]"r"((mips_reg)ref_stride)
);
/* clang-format on */
return sad;
}
@@ -493,9 +487,11 @@ static inline unsigned int vpx_sad_avg32x(const uint8_t *src, int src_stride,
unsigned int sad;
double ftmp1, ftmp2, ftmp3, ftmp4, ftmp5;
mips_reg l_counter = counter;
mips_reg l_second_pred = (mips_reg)second_pred;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"pxor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"1: \n\t"
// Include two loop body, to reduce loop time.
SAD_SRC_AVGREF_ABS_SUB_32
@@ -512,11 +508,12 @@ static inline unsigned int vpx_sad_avg32x(const uint8_t *src, int src_stride,
: [ftmp1]"=&f"(ftmp1), [ftmp2]"=&f"(ftmp2), [ftmp3]"=&f"(ftmp3),
[ftmp4]"=&f"(ftmp4), [ftmp5]"=&f"(ftmp5), [counter]"+&r"(l_counter),
[src]"+&r"(src), [ref]"+&r"(ref),
[second_pred]"+&r"((mips_reg)second_pred),
[second_pred]"+&r"(l_second_pred),
[sad]"=&r"(sad)
: [src_stride]"r"((mips_reg)src_stride),
[ref_stride]"r"((mips_reg)ref_stride)
);
/* clang-format on */
return sad;
}
@@ -539,8 +536,9 @@ static inline unsigned int vpx_sad16x(const uint8_t *src, int src_stride,
double ftmp1, ftmp2, ftmp3, ftmp4, ftmp5;
mips_reg l_counter = counter;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"pxor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"1: \n\t"
// Include two loop body, to reduce loop time.
SAD_SRC_REF_ABS_SUB_16
@@ -558,6 +556,7 @@ static inline unsigned int vpx_sad16x(const uint8_t *src, int src_stride,
: [src_stride]"r"((mips_reg)src_stride),
[ref_stride]"r"((mips_reg)ref_stride)
);
/* clang-format on */
return sad;
}
@@ -571,10 +570,6 @@ static inline unsigned int vpx_sad16x(const uint8_t *src, int src_stride,
vpx_sad16xN(32);
vpx_sad16xN(16);
vpx_sad16xN(8);
sadMxNxK_mmi(16, 16, 3);
sadMxNxK_mmi(16, 16, 8);
sadMxNxK_mmi(16, 8, 3);
sadMxNxK_mmi(16, 8, 8);
sadMxNx4D_mmi(16, 32);
sadMxNx4D_mmi(16, 16);
sadMxNx4D_mmi(16, 8);
@@ -586,9 +581,11 @@ static inline unsigned int vpx_sad_avg16x(const uint8_t *src, int src_stride,
unsigned int sad;
double ftmp1, ftmp2, ftmp3, ftmp4, ftmp5;
mips_reg l_counter = counter;
mips_reg l_second_pred = (mips_reg)second_pred;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"pxor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
"1: \n\t"
// Include two loop body, to reduce loop time.
SAD_SRC_AVGREF_ABS_SUB_16
@@ -605,11 +602,12 @@ static inline unsigned int vpx_sad_avg16x(const uint8_t *src, int src_stride,
: [ftmp1]"=&f"(ftmp1), [ftmp2]"=&f"(ftmp2), [ftmp3]"=&f"(ftmp3),
[ftmp4]"=&f"(ftmp4), [ftmp5]"=&f"(ftmp5), [counter]"+&r"(l_counter),
[src]"+&r"(src), [ref]"+&r"(ref),
[second_pred]"+&r"((mips_reg)second_pred),
[second_pred]"+&r"(l_second_pred),
[sad]"=&r"(sad)
: [src_stride]"r"((mips_reg)src_stride),
[ref_stride]"r"((mips_reg)ref_stride)
);
/* clang-format on */
return sad;
}
@@ -632,8 +630,9 @@ static inline unsigned int vpx_sad8x(const uint8_t *src, int src_stride,
double ftmp1, ftmp2, ftmp3;
mips_reg l_counter = counter;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp3], %[ftmp3], %[ftmp3] \n\t"
"pxor %[ftmp3], %[ftmp3], %[ftmp3] \n\t"
"1: \n\t"
// Include two loop body, to reduce loop time.
SAD_SRC_REF_ABS_SUB_8
@@ -651,6 +650,7 @@ static inline unsigned int vpx_sad8x(const uint8_t *src, int src_stride,
: [src_stride]"r"((mips_reg)src_stride),
[ref_stride]"r"((mips_reg)ref_stride)
);
/* clang-format on */
return sad;
}
@@ -664,10 +664,6 @@ static inline unsigned int vpx_sad8x(const uint8_t *src, int src_stride,
vpx_sad8xN(16);
vpx_sad8xN(8);
vpx_sad8xN(4);
sadMxNxK_mmi(8, 16, 3);
sadMxNxK_mmi(8, 16, 8);
sadMxNxK_mmi(8, 8, 3);
sadMxNxK_mmi(8, 8, 8);
sadMxNx4D_mmi(8, 16);
sadMxNx4D_mmi(8, 8);
sadMxNx4D_mmi(8, 4);
@@ -679,9 +675,11 @@ static inline unsigned int vpx_sad_avg8x(const uint8_t *src, int src_stride,
unsigned int sad;
double ftmp1, ftmp2, ftmp3;
mips_reg l_counter = counter;
mips_reg l_second_pred = (mips_reg)second_pred;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp3], %[ftmp3], %[ftmp3] \n\t"
"pxor %[ftmp3], %[ftmp3], %[ftmp3] \n\t"
"1: \n\t"
// Include two loop body, to reduce loop time.
SAD_SRC_AVGREF_ABS_SUB_8
@@ -697,11 +695,12 @@ static inline unsigned int vpx_sad_avg8x(const uint8_t *src, int src_stride,
"mfc1 %[sad], %[ftmp3] \n\t"
: [ftmp1]"=&f"(ftmp1), [ftmp2]"=&f"(ftmp2), [ftmp3]"=&f"(ftmp3),
[counter]"+&r"(l_counter), [src]"+&r"(src), [ref]"+&r"(ref),
[second_pred]"+&r"((mips_reg)second_pred),
[second_pred]"+&r"(l_second_pred),
[sad]"=&r"(sad)
: [src_stride]"r"((mips_reg)src_stride),
[ref_stride]"r"((mips_reg)ref_stride)
);
/* clang-format on */
return sad;
}
@@ -724,8 +723,9 @@ static inline unsigned int vpx_sad4x(const uint8_t *src, int src_stride,
double ftmp1, ftmp2, ftmp3;
mips_reg l_counter = counter;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp3], %[ftmp3], %[ftmp3] \n\t"
"pxor %[ftmp3], %[ftmp3], %[ftmp3] \n\t"
"1: \n\t"
// Include two loop body, to reduce loop time.
SAD_SRC_REF_ABS_SUB_4
@@ -743,6 +743,7 @@ static inline unsigned int vpx_sad4x(const uint8_t *src, int src_stride,
: [src_stride]"r"((mips_reg)src_stride),
[ref_stride]"r"((mips_reg)ref_stride)
);
/* clang-format on */
return sad;
}
@@ -755,8 +756,6 @@ static inline unsigned int vpx_sad4x(const uint8_t *src, int src_stride,
vpx_sad4xN(8);
vpx_sad4xN(4);
sadMxNxK_mmi(4, 4, 3);
sadMxNxK_mmi(4, 4, 8);
sadMxNx4D_mmi(4, 8);
sadMxNx4D_mmi(4, 4);
@@ -767,9 +766,11 @@ static inline unsigned int vpx_sad_avg4x(const uint8_t *src, int src_stride,
unsigned int sad;
double ftmp1, ftmp2, ftmp3;
mips_reg l_counter = counter;
mips_reg l_second_pred = (mips_reg)second_pred;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp3], %[ftmp3], %[ftmp3] \n\t"
"pxor %[ftmp3], %[ftmp3], %[ftmp3] \n\t"
"1: \n\t"
// Include two loop body, to reduce loop time.
SAD_SRC_AVGREF_ABS_SUB_4
@@ -785,11 +786,12 @@ static inline unsigned int vpx_sad_avg4x(const uint8_t *src, int src_stride,
"mfc1 %[sad], %[ftmp3] \n\t"
: [ftmp1]"=&f"(ftmp1), [ftmp2]"=&f"(ftmp2), [ftmp3]"=&f"(ftmp3),
[counter]"+&r"(l_counter), [src]"+&r"(src), [ref]"+&r"(ref),
[second_pred]"+&r"((mips_reg)second_pred),
[second_pred]"+&r"(l_second_pred),
[sad]"=&r"(sad)
: [src_stride]"r"((mips_reg)src_stride),
[ref_stride]"r"((mips_reg)ref_stride)
);
/* clang-format on */
return sad;
}
libs/libvpx/vpx_dsp/mips/sad_msa.c
+10 -436
View File
@@ -159,380 +159,6 @@ static uint32_t sad_64width_msa(const uint8_t *src, int32_t src_stride,
return sad;
}
static void sad_4width_x3_msa(const uint8_t *src_ptr, int32_t src_stride,
const uint8_t *ref_ptr, int32_t ref_stride,
int32_t height, uint32_t *sad_array) {
int32_t ht_cnt;
uint32_t src0, src1, src2, src3;
v16u8 src = { 0 };
v16u8 ref = { 0 };
v16u8 ref0, ref1, ref2, ref3, diff;
v8u16 sad0 = { 0 };
v8u16 sad1 = { 0 };
v8u16 sad2 = { 0 };
for (ht_cnt = (height >> 2); ht_cnt--;) {
LW4(src_ptr, src_stride, src0, src1, src2, src3);
src_ptr += (4 * src_stride);
INSERT_W4_UB(src0, src1, src2, src3, src);
LD_UB4(ref_ptr, ref_stride, ref0, ref1, ref2, ref3);
ref_ptr += (4 * ref_stride);
SAD_INSVE_W4_UB(ref0, ref1, ref2, ref3, ref);
diff = __msa_asub_u_b(src, ref);
sad0 += __msa_hadd_u_h(diff, diff);
SLDI_B2_UB(ref0, ref1, ref0, ref1, ref0, ref1, 1);
SLDI_B2_UB(ref2, ref3, ref2, ref3, ref2, ref3, 1);
SAD_INSVE_W4_UB(ref0, ref1, ref2, ref3, ref);
diff = __msa_asub_u_b(src, ref);
sad1 += __msa_hadd_u_h(diff, diff);
SLDI_B2_UB(ref0, ref1, ref0, ref1, ref0, ref1, 1);
SLDI_B2_UB(ref2, ref3, ref2, ref3, ref2, ref3, 1);
SAD_INSVE_W4_UB(ref0, ref1, ref2, ref3, ref);
diff = __msa_asub_u_b(src, ref);
sad2 += __msa_hadd_u_h(diff, diff);
}
sad_array[0] = HADD_UH_U32(sad0);
sad_array[1] = HADD_UH_U32(sad1);
sad_array[2] = HADD_UH_U32(sad2);
}
static void sad_8width_x3_msa(const uint8_t *src, int32_t src_stride,
const uint8_t *ref, int32_t ref_stride,
int32_t height, uint32_t *sad_array) {
int32_t ht_cnt;
v16u8 src0, src1, src2, src3;
v16u8 ref0, ref1, ref00, ref11, ref22, ref33;
v8u16 sad0 = { 0 };
v8u16 sad1 = { 0 };
v8u16 sad2 = { 0 };
for (ht_cnt = (height >> 2); ht_cnt--;) {
LD_UB4(src, src_stride, src0, src1, src2, src3);
src += (4 * src_stride);
LD_UB4(ref, ref_stride, ref00, ref11, ref22, ref33);
ref += (4 * ref_stride);
PCKEV_D4_UB(src1, src0, src3, src2, ref11, ref00, ref33, ref22, src0, src1,
ref0, ref1);
sad0 += SAD_UB2_UH(src0, src1, ref0, ref1);
SLDI_B2_UB(ref00, ref11, ref00, ref11, ref00, ref11, 1);
SLDI_B2_UB(ref22, ref33, ref22, ref33, ref22, ref33, 1);
PCKEV_D2_UB(ref11, ref00, ref33, ref22, ref0, ref1);
sad1 += SAD_UB2_UH(src0, src1, ref0, ref1);
SLDI_B2_UB(ref00, ref11, ref00, ref11, ref00, ref11, 1);
SLDI_B2_UB(ref22, ref33, ref22, ref33, ref22, ref33, 1);
PCKEV_D2_UB(ref11, ref00, ref33, ref22, ref0, ref1);
sad2 += SAD_UB2_UH(src0, src1, ref0, ref1);
}
sad_array[0] = HADD_UH_U32(sad0);
sad_array[1] = HADD_UH_U32(sad1);
sad_array[2] = HADD_UH_U32(sad2);
}
static void sad_16width_x3_msa(const uint8_t *src_ptr, int32_t src_stride,
const uint8_t *ref_ptr, int32_t ref_stride,
int32_t height, uint32_t *sad_array) {
int32_t ht_cnt;
v16u8 src, ref, ref0, ref1, diff;
v8u16 sad0 = { 0 };
v8u16 sad1 = { 0 };
v8u16 sad2 = { 0 };
for (ht_cnt = (height >> 1); ht_cnt--;) {
src = LD_UB(src_ptr);
src_ptr += src_stride;
LD_UB2(ref_ptr, 16, ref0, ref1);
ref_ptr += ref_stride;
diff = __msa_asub_u_b(src, ref0);
sad0 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 1);
diff = __msa_asub_u_b(src, ref);
sad1 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 2);
diff = __msa_asub_u_b(src, ref);
sad2 += __msa_hadd_u_h(diff, diff);
src = LD_UB(src_ptr);
src_ptr += src_stride;
LD_UB2(ref_ptr, 16, ref0, ref1);
ref_ptr += ref_stride;
diff = __msa_asub_u_b(src, ref0);
sad0 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 1);
diff = __msa_asub_u_b(src, ref);
sad1 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 2);
diff = __msa_asub_u_b(src, ref);
sad2 += __msa_hadd_u_h(diff, diff);
}
sad_array[0] = HADD_UH_U32(sad0);
sad_array[1] = HADD_UH_U32(sad1);
sad_array[2] = HADD_UH_U32(sad2);
}
static void sad_4width_x8_msa(const uint8_t *src_ptr, int32_t src_stride,
const uint8_t *ref_ptr, int32_t ref_stride,
int32_t height, uint32_t *sad_array) {
int32_t ht_cnt;
uint32_t src0, src1, src2, src3;
v16u8 ref0, ref1, ref2, ref3, diff;
v16u8 src = { 0 };
v16u8 ref = { 0 };
v8u16 sad0 = { 0 };
v8u16 sad1 = { 0 };
v8u16 sad2 = { 0 };
v8u16 sad3 = { 0 };
v8u16 sad4 = { 0 };
v8u16 sad5 = { 0 };
v8u16 sad6 = { 0 };
v8u16 sad7 = { 0 };
for (ht_cnt = (height >> 2); ht_cnt--;) {
LW4(src_ptr, src_stride, src0, src1, src2, src3);
INSERT_W4_UB(src0, src1, src2, src3, src);
src_ptr += (4 * src_stride);
LD_UB4(ref_ptr, ref_stride, ref0, ref1, ref2, ref3);
ref_ptr += (4 * ref_stride);
SAD_INSVE_W4_UB(ref0, ref1, ref2, ref3, ref);
diff = __msa_asub_u_b(src, ref);
sad0 += __msa_hadd_u_h(diff, diff);
SLDI_B2_UB(ref0, ref1, ref0, ref1, ref0, ref1, 1);
SLDI_B2_UB(ref2, ref3, ref2, ref3, ref2, ref3, 1);
SAD_INSVE_W4_UB(ref0, ref1, ref2, ref3, ref);
diff = __msa_asub_u_b(src, ref);
sad1 += __msa_hadd_u_h(diff, diff);
SLDI_B2_UB(ref0, ref1, ref0, ref1, ref0, ref1, 1);
SLDI_B2_UB(ref2, ref3, ref2, ref3, ref2, ref3, 1);
SAD_INSVE_W4_UB(ref0, ref1, ref2, ref3, ref);
diff = __msa_asub_u_b(src, ref);
sad2 += __msa_hadd_u_h(diff, diff);
SLDI_B2_UB(ref0, ref1, ref0, ref1, ref0, ref1, 1);
SLDI_B2_UB(ref2, ref3, ref2, ref3, ref2, ref3, 1);
SAD_INSVE_W4_UB(ref0, ref1, ref2, ref3, ref);
diff = __msa_asub_u_b(src, ref);
sad3 += __msa_hadd_u_h(diff, diff);
SLDI_B2_UB(ref0, ref1, ref0, ref1, ref0, ref1, 1);
SLDI_B2_UB(ref2, ref3, ref2, ref3, ref2, ref3, 1);
SAD_INSVE_W4_UB(ref0, ref1, ref2, ref3, ref);
diff = __msa_asub_u_b(src, ref);
sad4 += __msa_hadd_u_h(diff, diff);
SLDI_B2_UB(ref0, ref1, ref0, ref1, ref0, ref1, 1);
SLDI_B2_UB(ref2, ref3, ref2, ref3, ref2, ref3, 1);
SAD_INSVE_W4_UB(ref0, ref1, ref2, ref3, ref);
diff = __msa_asub_u_b(src, ref);
sad5 += __msa_hadd_u_h(diff, diff);
SLDI_B2_UB(ref0, ref1, ref0, ref1, ref0, ref1, 1);
SLDI_B2_UB(ref2, ref3, ref2, ref3, ref2, ref3, 1);
SAD_INSVE_W4_UB(ref0, ref1, ref2, ref3, ref);
diff = __msa_asub_u_b(src, ref);
sad6 += __msa_hadd_u_h(diff, diff);
SLDI_B2_UB(ref0, ref1, ref0, ref1, ref0, ref1, 1);
SLDI_B2_UB(ref2, ref3, ref2, ref3, ref2, ref3, 1);
SAD_INSVE_W4_UB(ref0, ref1, ref2, ref3, ref);
diff = __msa_asub_u_b(src, ref);
sad7 += __msa_hadd_u_h(diff, diff);
}
sad_array[0] = HADD_UH_U32(sad0);
sad_array[1] = HADD_UH_U32(sad1);
sad_array[2] = HADD_UH_U32(sad2);
sad_array[3] = HADD_UH_U32(sad3);
sad_array[4] = HADD_UH_U32(sad4);
sad_array[5] = HADD_UH_U32(sad5);
sad_array[6] = HADD_UH_U32(sad6);
sad_array[7] = HADD_UH_U32(sad7);
}
static void sad_8width_x8_msa(const uint8_t *src, int32_t src_stride,
const uint8_t *ref, int32_t ref_stride,
int32_t height, uint32_t *sad_array) {
int32_t ht_cnt;
v16u8 src0, src1, src2, src3;
v16u8 ref0, ref1, ref00, ref11, ref22, ref33;
v8u16 sad0 = { 0 };
v8u16 sad1 = { 0 };
v8u16 sad2 = { 0 };
v8u16 sad3 = { 0 };
v8u16 sad4 = { 0 };
v8u16 sad5 = { 0 };
v8u16 sad6 = { 0 };
v8u16 sad7 = { 0 };
for (ht_cnt = (height >> 2); ht_cnt--;) {
LD_UB4(src, src_stride, src0, src1, src2, src3);
src += (4 * src_stride);
LD_UB4(ref, ref_stride, ref00, ref11, ref22, ref33);
ref += (4 * ref_stride);
PCKEV_D4_UB(src1, src0, src3, src2, ref11, ref00, ref33, ref22, src0, src1,
ref0, ref1);
sad0 += SAD_UB2_UH(src0, src1, ref0, ref1);
SLDI_B2_UB(ref00, ref11, ref00, ref11, ref00, ref11, 1);
SLDI_B2_UB(ref22, ref33, ref22, ref33, ref22, ref33, 1);
PCKEV_D2_UB(ref11, ref00, ref33, ref22, ref0, ref1);
sad1 += SAD_UB2_UH(src0, src1, ref0, ref1);
SLDI_B2_UB(ref00, ref11, ref00, ref11, ref00, ref11, 1);
SLDI_B2_UB(ref22, ref33, ref22, ref33, ref22, ref33, 1);
PCKEV_D2_UB(ref11, ref00, ref33, ref22, ref0, ref1);
sad2 += SAD_UB2_UH(src0, src1, ref0, ref1);
SLDI_B2_UB(ref00, ref11, ref00, ref11, ref00, ref11, 1);
SLDI_B2_UB(ref22, ref33, ref22, ref33, ref22, ref33, 1);
PCKEV_D2_UB(ref11, ref00, ref33, ref22, ref0, ref1);
sad3 += SAD_UB2_UH(src0, src1, ref0, ref1);
SLDI_B2_UB(ref00, ref11, ref00, ref11, ref00, ref11, 1);
SLDI_B2_UB(ref22, ref33, ref22, ref33, ref22, ref33, 1);
PCKEV_D2_UB(ref11, ref00, ref33, ref22, ref0, ref1);
sad4 += SAD_UB2_UH(src0, src1, ref0, ref1);
SLDI_B2_UB(ref00, ref11, ref00, ref11, ref00, ref11, 1);
SLDI_B2_UB(ref22, ref33, ref22, ref33, ref22, ref33, 1);
PCKEV_D2_UB(ref11, ref00, ref33, ref22, ref0, ref1);
sad5 += SAD_UB2_UH(src0, src1, ref0, ref1);
SLDI_B2_UB(ref00, ref11, ref00, ref11, ref00, ref11, 1);
SLDI_B2_UB(ref22, ref33, ref22, ref33, ref22, ref33, 1);
PCKEV_D2_UB(ref11, ref00, ref33, ref22, ref0, ref1);
sad6 += SAD_UB2_UH(src0, src1, ref0, ref1);
SLDI_B2_UB(ref00, ref11, ref00, ref11, ref00, ref11, 1);
SLDI_B2_UB(ref22, ref33, ref22, ref33, ref22, ref33, 1);
PCKEV_D2_UB(ref11, ref00, ref33, ref22, ref0, ref1);
sad7 += SAD_UB2_UH(src0, src1, ref0, ref1);
}
sad_array[0] = HADD_UH_U32(sad0);
sad_array[1] = HADD_UH_U32(sad1);
sad_array[2] = HADD_UH_U32(sad2);
sad_array[3] = HADD_UH_U32(sad3);
sad_array[4] = HADD_UH_U32(sad4);
sad_array[5] = HADD_UH_U32(sad5);
sad_array[6] = HADD_UH_U32(sad6);
sad_array[7] = HADD_UH_U32(sad7);
}
static void sad_16width_x8_msa(const uint8_t *src_ptr, int32_t src_stride,
const uint8_t *ref_ptr, int32_t ref_stride,
int32_t height, uint32_t *sad_array) {
int32_t ht_cnt;
v16u8 src, ref0, ref1, ref;
v16u8 diff;
v8u16 sad0 = { 0 };
v8u16 sad1 = { 0 };
v8u16 sad2 = { 0 };
v8u16 sad3 = { 0 };
v8u16 sad4 = { 0 };
v8u16 sad5 = { 0 };
v8u16 sad6 = { 0 };
v8u16 sad7 = { 0 };
for (ht_cnt = (height >> 1); ht_cnt--;) {
src = LD_UB(src_ptr);
src_ptr += src_stride;
LD_UB2(ref_ptr, 16, ref0, ref1);
ref_ptr += ref_stride;
diff = __msa_asub_u_b(src, ref0);
sad0 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 1);
diff = __msa_asub_u_b(src, ref);
sad1 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 2);
diff = __msa_asub_u_b(src, ref);
sad2 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 3);
diff = __msa_asub_u_b(src, ref);
sad3 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 4);
diff = __msa_asub_u_b(src, ref);
sad4 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 5);
diff = __msa_asub_u_b(src, ref);
sad5 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 6);
diff = __msa_asub_u_b(src, ref);
sad6 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 7);
diff = __msa_asub_u_b(src, ref);
sad7 += __msa_hadd_u_h(diff, diff);
src = LD_UB(src_ptr);
src_ptr += src_stride;
LD_UB2(ref_ptr, 16, ref0, ref1);
ref_ptr += ref_stride;
diff = __msa_asub_u_b(src, ref0);
sad0 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 1);
diff = __msa_asub_u_b(src, ref);
sad1 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 2);
diff = __msa_asub_u_b(src, ref);
sad2 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 3);
diff = __msa_asub_u_b(src, ref);
sad3 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 4);
diff = __msa_asub_u_b(src, ref);
sad4 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 5);
diff = __msa_asub_u_b(src, ref);
sad5 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 6);
diff = __msa_asub_u_b(src, ref);
sad6 += __msa_hadd_u_h(diff, diff);
ref = (v16u8)__msa_sldi_b((v16i8)ref1, (v16i8)ref0, 7);
diff = __msa_asub_u_b(src, ref);
sad7 += __msa_hadd_u_h(diff, diff);
}
sad_array[0] = HADD_UH_U32(sad0);
sad_array[1] = HADD_UH_U32(sad1);
sad_array[2] = HADD_UH_U32(sad2);
sad_array[3] = HADD_UH_U32(sad3);
sad_array[4] = HADD_UH_U32(sad4);
sad_array[5] = HADD_UH_U32(sad5);
sad_array[6] = HADD_UH_U32(sad6);
sad_array[7] = HADD_UH_U32(sad7);
}
static void sad_4width_x4d_msa(const uint8_t *src_ptr, int32_t src_stride,
const uint8_t *const aref_ptr[],
int32_t ref_stride, int32_t height,
@@ -1037,80 +663,38 @@ static uint32_t avgsad_64width_msa(const uint8_t *src, int32_t src_stride,
return sad_64width_msa(src, src_stride, ref, ref_stride, height); \
}
#define VPX_SAD_4xHEIGHTx3_MSA(height) \
void vpx_sad4x##height##x3_msa(const uint8_t *src, int32_t src_stride, \
const uint8_t *ref, int32_t ref_stride, \
uint32_t *sads) { \
sad_4width_x3_msa(src, src_stride, ref, ref_stride, height, sads); \
}
#define VPX_SAD_8xHEIGHTx3_MSA(height) \
void vpx_sad8x##height##x3_msa(const uint8_t *src, int32_t src_stride, \
const uint8_t *ref, int32_t ref_stride, \
uint32_t *sads) { \
sad_8width_x3_msa(src, src_stride, ref, ref_stride, height, sads); \
}
#define VPX_SAD_16xHEIGHTx3_MSA(height) \
void vpx_sad16x##height##x3_msa(const uint8_t *src, int32_t src_stride, \
const uint8_t *ref, int32_t ref_stride, \
uint32_t *sads) { \
sad_16width_x3_msa(src, src_stride, ref, ref_stride, height, sads); \
}
#define VPX_SAD_4xHEIGHTx8_MSA(height) \
void vpx_sad4x##height##x8_msa(const uint8_t *src, int32_t src_stride, \
const uint8_t *ref, int32_t ref_stride, \
uint32_t *sads) { \
sad_4width_x8_msa(src, src_stride, ref, ref_stride, height, sads); \
}
#define VPX_SAD_8xHEIGHTx8_MSA(height) \
void vpx_sad8x##height##x8_msa(const uint8_t *src, int32_t src_stride, \
const uint8_t *ref, int32_t ref_stride, \
uint32_t *sads) { \
sad_8width_x8_msa(src, src_stride, ref, ref_stride, height, sads); \
}
#define VPX_SAD_16xHEIGHTx8_MSA(height) \
void vpx_sad16x##height##x8_msa(const uint8_t *src, int32_t src_stride, \
const uint8_t *ref, int32_t ref_stride, \
uint32_t *sads) { \
sad_16width_x8_msa(src, src_stride, ref, ref_stride, height, sads); \
}
#define VPX_SAD_4xHEIGHTx4D_MSA(height) \
void vpx_sad4x##height##x4d_msa(const uint8_t *src, int32_t src_stride, \
const uint8_t *const refs[], \
int32_t ref_stride, uint32_t *sads) { \
const uint8_t *const refs[4], \
int32_t ref_stride, uint32_t sads[4]) { \
sad_4width_x4d_msa(src, src_stride, refs, ref_stride, height, sads); \
}
#define VPX_SAD_8xHEIGHTx4D_MSA(height) \
void vpx_sad8x##height##x4d_msa(const uint8_t *src, int32_t src_stride, \
const uint8_t *const refs[], \
int32_t ref_stride, uint32_t *sads) { \
const uint8_t *const refs[4], \
int32_t ref_stride, uint32_t sads[4]) { \
sad_8width_x4d_msa(src, src_stride, refs, ref_stride, height, sads); \
}
#define VPX_SAD_16xHEIGHTx4D_MSA(height) \
void vpx_sad16x##height##x4d_msa(const uint8_t *src, int32_t src_stride, \
const uint8_t *const refs[], \
int32_t ref_stride, uint32_t *sads) { \
const uint8_t *const refs[4], \
int32_t ref_stride, uint32_t sads[4]) { \
sad_16width_x4d_msa(src, src_stride, refs, ref_stride, height, sads); \
}
#define VPX_SAD_32xHEIGHTx4D_MSA(height) \
void vpx_sad32x##height##x4d_msa(const uint8_t *src, int32_t src_stride, \
const uint8_t *const refs[], \
int32_t ref_stride, uint32_t *sads) { \
const uint8_t *const refs[4], \
int32_t ref_stride, uint32_t sads[4]) { \
sad_32width_x4d_msa(src, src_stride, refs, ref_stride, height, sads); \
}
#define VPX_SAD_64xHEIGHTx4D_MSA(height) \
void vpx_sad64x##height##x4d_msa(const uint8_t *src, int32_t src_stride, \
const uint8_t *const refs[], \
int32_t ref_stride, uint32_t *sads) { \
const uint8_t *const refs[4], \
int32_t ref_stride, uint32_t sads[4]) { \
sad_64width_x4d_msa(src, src_stride, refs, ref_stride, height, sads); \
}
@@ -1186,29 +770,21 @@ VPX_AVGSAD_16xHEIGHT_MSA(32);
// 16x16
VPX_SAD_16xHEIGHT_MSA(16);
VPX_SAD_16xHEIGHTx3_MSA(16);
VPX_SAD_16xHEIGHTx8_MSA(16);
VPX_SAD_16xHEIGHTx4D_MSA(16);
VPX_AVGSAD_16xHEIGHT_MSA(16);
// 16x8
VPX_SAD_16xHEIGHT_MSA(8);
VPX_SAD_16xHEIGHTx3_MSA(8);
VPX_SAD_16xHEIGHTx8_MSA(8);
VPX_SAD_16xHEIGHTx4D_MSA(8);
VPX_AVGSAD_16xHEIGHT_MSA(8);
// 8x16
VPX_SAD_8xHEIGHT_MSA(16);
VPX_SAD_8xHEIGHTx3_MSA(16);
VPX_SAD_8xHEIGHTx8_MSA(16);
VPX_SAD_8xHEIGHTx4D_MSA(16);
VPX_AVGSAD_8xHEIGHT_MSA(16);
// 8x8
VPX_SAD_8xHEIGHT_MSA(8);
VPX_SAD_8xHEIGHTx3_MSA(8);
VPX_SAD_8xHEIGHTx8_MSA(8);
VPX_SAD_8xHEIGHTx4D_MSA(8);
VPX_AVGSAD_8xHEIGHT_MSA(8);
@@ -1224,7 +800,5 @@ VPX_AVGSAD_4xHEIGHT_MSA(8);
// 4x4
VPX_SAD_4xHEIGHT_MSA(4);
VPX_SAD_4xHEIGHTx3_MSA(4);
VPX_SAD_4xHEIGHTx8_MSA(4);
VPX_SAD_4xHEIGHTx4D_MSA(4);
VPX_AVGSAD_4xHEIGHT_MSA(4);
libs/libvpx/vpx_dsp/mips/subtract_mmi.c
+3 -3
View File
@@ -24,7 +24,7 @@ void vpx_subtract_block_mmi(int rows, int cols, int16_t *diff,
switch (rows) {
case 4:
__asm__ volatile(
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
#if _MIPS_SIM == _ABIO32
"ulw %[tmp0], 0x00(%[src]) \n\t"
"mtc1 %[tmp0], %[ftmp1] \n\t"
@@ -118,7 +118,7 @@ void vpx_subtract_block_mmi(int rows, int cols, int16_t *diff,
break;
case 8:
__asm__ volatile(
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"li %[tmp0], 0x02 \n\t"
"1: \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
@@ -206,7 +206,7 @@ void vpx_subtract_block_mmi(int rows, int cols, int16_t *diff,
break;
case 16:
__asm__ volatile(
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"li %[tmp0], 0x08 \n\t"
"1: \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src]) \n\t"
libs/libvpx/vpx_dsp/mips/variance_mmi.c
+157 -91
View File
@@ -150,7 +150,7 @@ static const uint8_t bilinear_filters[8][2] = {
"psrlh %[ftmp2], %[ftmp2], %[ftmp6] \n\t" \
\
/* store: temp2[0] ~ temp2[3] */ \
"and %[ftmp2], %[ftmp2], %[mask] \n\t" \
"pand %[ftmp2], %[ftmp2], %[mask] \n\t" \
"packushb %[ftmp2], %[ftmp2], %[ftmp0] \n\t" \
"gssdrc1 %[ftmp2], 0x00(%[temp2_ptr]) \n\t"
@@ -163,7 +163,7 @@ static const uint8_t bilinear_filters[8][2] = {
"psrlh %[ftmp4], %[ftmp4], %[ftmp6] \n\t" \
\
/* store: temp2[0] ~ temp2[3] */ \
"and %[ftmp4], %[ftmp4], %[mask] \n\t" \
"pand %[ftmp4], %[ftmp4], %[mask] \n\t" \
"packushb %[ftmp4], %[ftmp4], %[ftmp0] \n\t" \
"gssdrc1 %[ftmp4], 0x00(%[temp2_ptr]) \n\t"
@@ -225,8 +225,8 @@ static const uint8_t bilinear_filters[8][2] = {
"psrlh %[ftmp3], %[ftmp3], %[ftmp14] \n\t" \
\
/* store: temp2[0] ~ temp2[7] */ \
"and %[ftmp2], %[ftmp2], %[mask] \n\t" \
"and %[ftmp3], %[ftmp3], %[mask] \n\t" \
"pand %[ftmp2], %[ftmp2], %[mask] \n\t" \
"pand %[ftmp3], %[ftmp3], %[mask] \n\t" \
"packushb %[ftmp2], %[ftmp2], %[ftmp3] \n\t" \
"gssdlc1 %[ftmp2], 0x07(%[temp2_ptr]) \n\t" \
"gssdrc1 %[ftmp2], 0x00(%[temp2_ptr]) \n\t"
@@ -247,8 +247,8 @@ static const uint8_t bilinear_filters[8][2] = {
"psrlh %[ftmp9], %[ftmp9], %[ftmp14] \n\t" \
\
/* store: temp2[0] ~ temp2[7] */ \
"and %[ftmp8], %[ftmp8], %[mask] \n\t" \
"and %[ftmp9], %[ftmp9], %[mask] \n\t" \
"pand %[ftmp8], %[ftmp8], %[mask] \n\t" \
"pand %[ftmp9], %[ftmp9], %[mask] \n\t" \
"packushb %[ftmp8], %[ftmp8], %[ftmp9] \n\t" \
"gssdlc1 %[ftmp8], 0x07(%[temp2_ptr]) \n\t" \
"gssdrc1 %[ftmp8], 0x00(%[temp2_ptr]) \n\t"
@@ -319,8 +319,8 @@ static const uint8_t bilinear_filters[8][2] = {
"psrlh %[ftmp5], %[ftmp5], %[ftmp14] \n\t" \
\
/* store: temp2[8] ~ temp2[15] */ \
"and %[ftmp4], %[ftmp4], %[mask] \n\t" \
"and %[ftmp5], %[ftmp5], %[mask] \n\t" \
"pand %[ftmp4], %[ftmp4], %[mask] \n\t" \
"pand %[ftmp5], %[ftmp5], %[mask] \n\t" \
"packushb %[ftmp4], %[ftmp4], %[ftmp5] \n\t" \
"gssdlc1 %[ftmp4], 0x0f(%[temp2_ptr]) \n\t" \
"gssdrc1 %[ftmp4], 0x08(%[temp2_ptr]) \n\t"
@@ -343,8 +343,8 @@ static const uint8_t bilinear_filters[8][2] = {
"psrlh %[ftmp11], %[ftmp11], %[ftmp14] \n\t" \
\
/* store: temp2[8] ~ temp2[15] */ \
"and %[ftmp10], %[ftmp10], %[mask] \n\t" \
"and %[ftmp11], %[ftmp11], %[mask] \n\t" \
"pand %[ftmp10], %[ftmp10], %[mask] \n\t" \
"pand %[ftmp11], %[ftmp11], %[mask] \n\t" \
"packushb %[ftmp10], %[ftmp10], %[ftmp11] \n\t" \
"gssdlc1 %[ftmp10], 0x0f(%[temp2_ptr]) \n\t" \
"gssdrc1 %[ftmp10], 0x08(%[temp2_ptr]) \n\t"
@@ -414,13 +414,14 @@ static inline uint32_t vpx_variance64x(const uint8_t *src_ptr, int src_stride,
*sse = 0;
/* clang-format off */
__asm__ volatile (
"li %[tmp0], 0x20 \n\t"
"mtc1 %[tmp0], %[ftmp11] \n\t"
MMI_L(%[tmp0], %[high], 0x00)
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"xor %[ftmp9], %[ftmp9], %[ftmp9] \n\t"
"xor %[ftmp10], %[ftmp10], %[ftmp10] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp9], %[ftmp9], %[ftmp9] \n\t"
"pxor %[ftmp10], %[ftmp10], %[ftmp10] \n\t"
"1: \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src_ptr]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src_ptr]) \n\t"
@@ -478,7 +479,7 @@ static inline uint32_t vpx_variance64x(const uint8_t *src_ptr, int src_stride,
"mfc1 %[tmp1], %[ftmp9] \n\t"
"mfhc1 %[tmp2], %[ftmp9] \n\t"
"addu %[sum], %[tmp1], %[tmp2] \n\t"
"dsrl %[ftmp1], %[ftmp10], %[ftmp11] \n\t"
"ssrld %[ftmp1], %[ftmp10], %[ftmp11] \n\t"
"paddw %[ftmp1], %[ftmp1], %[ftmp10] \n\t"
"swc1 %[ftmp1], 0x00(%[sse]) \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
@@ -496,6 +497,7 @@ static inline uint32_t vpx_variance64x(const uint8_t *src_ptr, int src_stride,
[high]"r"(&high), [sse]"r"(sse)
: "memory"
);
/* clang-format on */
return *sse - (((int64_t)sum * sum) / (64 * high));
}
@@ -519,13 +521,14 @@ uint32_t vpx_variance32x64_mmi(const uint8_t *src_ptr, int src_stride,
*sse = 0;
/* clang-format off */
__asm__ volatile (
"li %[tmp0], 0x20 \n\t"
"mtc1 %[tmp0], %[ftmp11] \n\t"
"li %[tmp0], 0x40 \n\t"
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"xor %[ftmp9], %[ftmp9], %[ftmp9] \n\t"
"xor %[ftmp10], %[ftmp10], %[ftmp10] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp9], %[ftmp9], %[ftmp9] \n\t"
"pxor %[ftmp10], %[ftmp10], %[ftmp10] \n\t"
"1: \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src_ptr]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src_ptr]) \n\t"
@@ -559,7 +562,7 @@ uint32_t vpx_variance32x64_mmi(const uint8_t *src_ptr, int src_stride,
"mfc1 %[tmp1], %[ftmp9] \n\t"
"mfhc1 %[tmp2], %[ftmp9] \n\t"
"addu %[sum], %[tmp1], %[tmp2] \n\t"
"dsrl %[ftmp1], %[ftmp10], %[ftmp11] \n\t"
"ssrld %[ftmp1], %[ftmp10], %[ftmp11] \n\t"
"paddw %[ftmp1], %[ftmp1], %[ftmp10] \n\t"
"swc1 %[ftmp1], 0x00(%[sse]) \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
@@ -577,6 +580,7 @@ uint32_t vpx_variance32x64_mmi(const uint8_t *src_ptr, int src_stride,
[sse]"r"(sse)
: "memory"
);
/* clang-format on */
return *sse - (((int64_t)sum * sum) / 2048);
}
@@ -590,14 +594,15 @@ static inline uint32_t vpx_variance32x(const uint8_t *src_ptr, int src_stride,
*sse = 0;
/* clang-format off */
__asm__ volatile (
"li %[tmp0], 0x20 \n\t"
"mtc1 %[tmp0], %[ftmp11] \n\t"
MMI_L(%[tmp0], %[high], 0x00)
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"xor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"xor %[ftmp10], %[ftmp10], %[ftmp10] \n\t"
"xor %[ftmp12], %[ftmp12], %[ftmp12] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"pxor %[ftmp10], %[ftmp10], %[ftmp10] \n\t"
"pxor %[ftmp12], %[ftmp12], %[ftmp12] \n\t"
"1: \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src_ptr]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src_ptr]) \n\t"
@@ -625,7 +630,7 @@ static inline uint32_t vpx_variance32x(const uint8_t *src_ptr, int src_stride,
MMI_ADDU(%[ref_ptr], %[ref_ptr], %[ref_stride])
"bnez %[tmp0], 1b \n\t"
"dsrl %[ftmp9], %[ftmp8], %[ftmp11] \n\t"
"ssrld %[ftmp9], %[ftmp8], %[ftmp11] \n\t"
"paddw %[ftmp9], %[ftmp9], %[ftmp8] \n\t"
"swc1 %[ftmp9], 0x00(%[sse]) \n\t"
@@ -636,7 +641,7 @@ static inline uint32_t vpx_variance32x(const uint8_t *src_ptr, int src_stride,
"paddw %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"psubw %[ftmp3], %[ftmp3], %[ftmp5] \n\t"
"psubw %[ftmp3], %[ftmp3], %[ftmp6] \n\t"
"dsrl %[ftmp0], %[ftmp3], %[ftmp11] \n\t"
"ssrld %[ftmp0], %[ftmp3], %[ftmp11] \n\t"
"paddw %[ftmp0], %[ftmp0], %[ftmp3] \n\t"
"swc1 %[ftmp0], 0x00(%[sum]) \n\t"
@@ -653,6 +658,7 @@ static inline uint32_t vpx_variance32x(const uint8_t *src_ptr, int src_stride,
[high]"r"(&high), [sse]"r"(sse), [sum]"r"(&sum)
: "memory"
);
/* clang-format on */
return *sse - (((int64_t)sum * sum) / (32 * high));
}
@@ -676,14 +682,15 @@ static inline uint32_t vpx_variance16x(const uint8_t *src_ptr, int src_stride,
*sse = 0;
/* clang-format off */
__asm__ volatile (
"li %[tmp0], 0x20 \n\t"
"mtc1 %[tmp0], %[ftmp11] \n\t"
MMI_L(%[tmp0], %[high], 0x00)
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"xor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"xor %[ftmp10], %[ftmp10], %[ftmp10] \n\t"
"xor %[ftmp12], %[ftmp12], %[ftmp12] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"pxor %[ftmp10], %[ftmp10], %[ftmp10] \n\t"
"pxor %[ftmp12], %[ftmp12], %[ftmp12] \n\t"
"1: \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src_ptr]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src_ptr]) \n\t"
@@ -701,7 +708,7 @@ static inline uint32_t vpx_variance16x(const uint8_t *src_ptr, int src_stride,
MMI_ADDU(%[ref_ptr], %[ref_ptr], %[ref_stride])
"bnez %[tmp0], 1b \n\t"
"dsrl %[ftmp9], %[ftmp8], %[ftmp11] \n\t"
"ssrld %[ftmp9], %[ftmp8], %[ftmp11] \n\t"
"paddw %[ftmp9], %[ftmp9], %[ftmp8] \n\t"
"swc1 %[ftmp9], 0x00(%[sse]) \n\t"
@@ -712,7 +719,7 @@ static inline uint32_t vpx_variance16x(const uint8_t *src_ptr, int src_stride,
"paddw %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"psubw %[ftmp3], %[ftmp3], %[ftmp5] \n\t"
"psubw %[ftmp3], %[ftmp3], %[ftmp6] \n\t"
"dsrl %[ftmp0], %[ftmp3], %[ftmp11] \n\t"
"ssrld %[ftmp0], %[ftmp3], %[ftmp11] \n\t"
"paddw %[ftmp0], %[ftmp0], %[ftmp3] \n\t"
"swc1 %[ftmp0], 0x00(%[sum]) \n\t"
@@ -729,6 +736,7 @@ static inline uint32_t vpx_variance16x(const uint8_t *src_ptr, int src_stride,
[high]"r"(&high), [sse]"r"(sse), [sum]"r"(&sum)
: "memory"
);
/* clang-format on */
return *sse - (((int64_t)sum * sum) / (16 * high));
}
@@ -753,14 +761,15 @@ static inline uint32_t vpx_variance8x(const uint8_t *src_ptr, int src_stride,
*sse = 0;
/* clang-format off */
__asm__ volatile (
"li %[tmp0], 0x20 \n\t"
"mtc1 %[tmp0], %[ftmp11] \n\t"
MMI_L(%[tmp0], %[high], 0x00)
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"xor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"xor %[ftmp10], %[ftmp10], %[ftmp10] \n\t"
"xor %[ftmp12], %[ftmp12], %[ftmp12] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"pxor %[ftmp10], %[ftmp10], %[ftmp10] \n\t"
"pxor %[ftmp12], %[ftmp12], %[ftmp12] \n\t"
"1: \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src_ptr]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src_ptr]) \n\t"
@@ -773,7 +782,7 @@ static inline uint32_t vpx_variance8x(const uint8_t *src_ptr, int src_stride,
MMI_ADDU(%[ref_ptr], %[ref_ptr], %[ref_stride])
"bnez %[tmp0], 1b \n\t"
"dsrl %[ftmp9], %[ftmp8], %[ftmp11] \n\t"
"ssrld %[ftmp9], %[ftmp8], %[ftmp11] \n\t"
"paddw %[ftmp9], %[ftmp9], %[ftmp8] \n\t"
"swc1 %[ftmp9], 0x00(%[sse]) \n\t"
@@ -784,7 +793,7 @@ static inline uint32_t vpx_variance8x(const uint8_t *src_ptr, int src_stride,
"paddw %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"psubw %[ftmp3], %[ftmp3], %[ftmp5] \n\t"
"psubw %[ftmp3], %[ftmp3], %[ftmp6] \n\t"
"dsrl %[ftmp0], %[ftmp3], %[ftmp11] \n\t"
"ssrld %[ftmp0], %[ftmp3], %[ftmp11] \n\t"
"paddw %[ftmp0], %[ftmp0], %[ftmp3] \n\t"
"swc1 %[ftmp0], 0x00(%[sum]) \n\t"
@@ -801,6 +810,7 @@ static inline uint32_t vpx_variance8x(const uint8_t *src_ptr, int src_stride,
[high]"r"(&high), [sse]"r"(sse), [sum]"r"(&sum)
: "memory"
);
/* clang-format on */
return *sse - (((int64_t)sum * sum) / (8 * high));
}
@@ -825,14 +835,15 @@ static inline uint32_t vpx_variance4x(const uint8_t *src_ptr, int src_stride,
*sse = 0;
/* clang-format off */
__asm__ volatile (
"li %[tmp0], 0x20 \n\t"
"mtc1 %[tmp0], %[ftmp10] \n\t"
MMI_L(%[tmp0], %[high], 0x00)
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"xor %[ftmp6], %[ftmp6], %[ftmp6] \n\t"
"xor %[ftmp7], %[ftmp7], %[ftmp7] \n\t"
"xor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp6], %[ftmp6], %[ftmp6] \n\t"
"pxor %[ftmp7], %[ftmp7], %[ftmp7] \n\t"
"pxor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"1: \n\t"
"gsldlc1 %[ftmp1], 0x07(%[src_ptr]) \n\t"
"gsldrc1 %[ftmp1], 0x00(%[src_ptr]) \n\t"
@@ -845,7 +856,7 @@ static inline uint32_t vpx_variance4x(const uint8_t *src_ptr, int src_stride,
MMI_ADDU(%[ref_ptr], %[ref_ptr], %[ref_stride])
"bnez %[tmp0], 1b \n\t"
"dsrl %[ftmp9], %[ftmp6], %[ftmp10] \n\t"
"ssrld %[ftmp9], %[ftmp6], %[ftmp10] \n\t"
"paddw %[ftmp9], %[ftmp9], %[ftmp6] \n\t"
"swc1 %[ftmp9], 0x00(%[sse]) \n\t"
@@ -856,7 +867,7 @@ static inline uint32_t vpx_variance4x(const uint8_t *src_ptr, int src_stride,
"paddw %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
"psubw %[ftmp3], %[ftmp3], %[ftmp5] \n\t"
"psubw %[ftmp3], %[ftmp3], %[ftmp6] \n\t"
"dsrl %[ftmp0], %[ftmp3], %[ftmp10] \n\t"
"ssrld %[ftmp0], %[ftmp3], %[ftmp10] \n\t"
"paddw %[ftmp0], %[ftmp0], %[ftmp3] \n\t"
"swc1 %[ftmp0], 0x00(%[sum]) \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
@@ -872,6 +883,7 @@ static inline uint32_t vpx_variance4x(const uint8_t *src_ptr, int src_stride,
[high]"r"(&high), [sse]"r"(sse), [sum]"r"(&sum)
: "memory"
);
/* clang-format on */
return *sse - (((int64_t)sum * sum) / (4 * high));
}
@@ -894,12 +906,13 @@ static inline uint32_t vpx_mse16x(const uint8_t *src_ptr, int src_stride,
*sse = 0;
/* clang-format off */
__asm__ volatile (
"li %[tmp0], 0x20 \n\t"
"mtc1 %[tmp0], %[ftmp11] \n\t"
MMI_L(%[tmp0], %[high], 0x00)
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"xor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"1: \n\t"
VARIANCE_SSE_16
@@ -909,7 +922,7 @@ static inline uint32_t vpx_mse16x(const uint8_t *src_ptr, int src_stride,
MMI_ADDU(%[ref_ptr], %[ref_ptr], %[ref_stride])
"bnez %[tmp0], 1b \n\t"
"dsrl %[ftmp9], %[ftmp8], %[ftmp11] \n\t"
"ssrld %[ftmp9], %[ftmp8], %[ftmp11] \n\t"
"paddw %[ftmp9], %[ftmp9], %[ftmp8] \n\t"
"swc1 %[ftmp9], 0x00(%[sse]) \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
@@ -925,6 +938,7 @@ static inline uint32_t vpx_mse16x(const uint8_t *src_ptr, int src_stride,
[high]"r"(&high), [sse]"r"(sse)
: "memory"
);
/* clang-format on */
return *sse;
}
@@ -947,12 +961,13 @@ static inline uint32_t vpx_mse8x(const uint8_t *src_ptr, int src_stride,
*sse = 0;
/* clang-format off */
__asm__ volatile (
"li %[tmp0], 0x20 \n\t"
"mtc1 %[tmp0], %[ftmp11] \n\t"
MMI_L(%[tmp0], %[high], 0x00)
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"xor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
"1: \n\t"
VARIANCE_SSE_8
@@ -962,7 +977,7 @@ static inline uint32_t vpx_mse8x(const uint8_t *src_ptr, int src_stride,
MMI_ADDU(%[ref_ptr], %[ref_ptr], %[ref_stride])
"bnez %[tmp0], 1b \n\t"
"dsrl %[ftmp9], %[ftmp8], %[ftmp11] \n\t"
"ssrld %[ftmp9], %[ftmp8], %[ftmp11] \n\t"
"paddw %[ftmp9], %[ftmp9], %[ftmp8] \n\t"
"swc1 %[ftmp9], 0x00(%[sse]) \n\t"
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
@@ -978,6 +993,7 @@ static inline uint32_t vpx_mse8x(const uint8_t *src_ptr, int src_stride,
[high]"r"(&high), [sse]"r"(sse)
: "memory"
);
/* clang-format on */
return *sse;
}
@@ -1021,22 +1037,39 @@ static inline void var_filter_block2d_bil_16x(const uint8_t *src_ptr,
uint8_t *temp2_ptr = temp2;
mips_reg l_counter = counter;
double ftmp[15];
double ff_ph_40, mask;
double filter_x0, filter_x1, filter_y0, filter_y1;
mips_reg tmp[2];
DECLARE_ALIGNED(8, const uint64_t, ff_ph_40) = { 0x0040004000400040ULL };
DECLARE_ALIGNED(8, const uint64_t, mask) = { 0x00ff00ff00ff00ffULL };
uint64_t x0, x1, y0, y1, all;
const uint8_t *filter_x = bilinear_filters[x_offset];
const uint8_t *filter_y = bilinear_filters[y_offset];
x0 = (uint64_t)filter_x[0];
x1 = (uint64_t)filter_x[1];
y0 = (uint64_t)filter_y[0];
y1 = (uint64_t)filter_y[1];
all = x0 | x1 << 8 | y0 << 16 | y1 << 24;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
MMI_MTC1(%[all], %[ftmp14])
"punpcklbh %[ftmp14], %[ftmp14], %[ftmp0] \n\t"
"pshufh %[filter_x0], %[ftmp14], %[ftmp0] \n\t"
MMI_LI(%[tmp0], 0x10)
MMI_MTC1(%[tmp0], %[mask])
"ssrld %[ftmp14], %[ftmp14], %[mask] \n\t"
"pshufh %[filter_x1], %[ftmp14], %[ftmp0] \n\t"
"ssrld %[ftmp14], %[ftmp14], %[mask] \n\t"
"pshufh %[filter_y0], %[ftmp14], %[ftmp0] \n\t"
"ssrld %[ftmp14], %[ftmp14], %[mask] \n\t"
"pshufh %[filter_y1], %[ftmp14], %[ftmp0] \n\t"
MMI_LI(%[tmp0], 0x07)
MMI_MTC1(%[tmp0], %[ftmp14])
"pshufh %[filter_x0], %[filter_x0], %[ftmp0] \n\t"
"pshufh %[filter_x1], %[filter_x1], %[ftmp0] \n\t"
"pshufh %[filter_y0], %[filter_y0], %[ftmp0] \n\t"
"pshufh %[filter_y1], %[filter_y1], %[ftmp0] \n\t"
MMI_LI(%[tmp0], 0x0040004000400040)
MMI_MTC1(%[tmp0], %[ff_ph_40])
MMI_LI(%[tmp0], 0x00ff00ff00ff00ff)
MMI_MTC1(%[tmp0], %[mask])
// fdata3: fdata3[0] ~ fdata3[15]
VAR_FILTER_BLOCK2D_BIL_FIRST_PASS_16_A
@@ -1072,15 +1105,13 @@ static inline void var_filter_block2d_bil_16x(const uint8_t *src_ptr,
[ftmp11] "=&f"(ftmp[11]), [ftmp12] "=&f"(ftmp[12]),
[ftmp13] "=&f"(ftmp[13]), [ftmp14] "=&f"(ftmp[14]),
[tmp0] "=&r"(tmp[0]), [src_ptr] "+&r"(src_ptr), [temp2_ptr] "+&r"(temp2_ptr),
[counter]"+&r"(l_counter)
: [filter_x0] "f"((uint64_t)filter_x[0]),
[filter_x1] "f"((uint64_t)filter_x[1]),
[filter_y0] "f"((uint64_t)filter_y[0]),
[filter_y1] "f"((uint64_t)filter_y[1]),
[src_stride] "r"((mips_reg)src_stride), [ff_ph_40] "f"(ff_ph_40),
[mask] "f"(mask)
[counter]"+&r"(l_counter), [ff_ph_40] "=&f"(ff_ph_40), [mask] "=&f"(mask),
[filter_x0] "=&f"(filter_x0), [filter_x1] "=&f"(filter_x1),
[filter_y0] "=&f"(filter_y0), [filter_y1] "=&f"(filter_y1)
: [src_stride] "r"((mips_reg)src_stride), [all] "r"(all)
: "memory"
);
/* clang-format on */
}
#define SUBPIX_VAR16XN(H) \
@@ -1105,19 +1136,38 @@ static inline void var_filter_block2d_bil_8x(const uint8_t *src_ptr,
mips_reg l_counter = counter;
double ftmp[15];
mips_reg tmp[2];
DECLARE_ALIGNED(8, const uint64_t, ff_ph_40) = { 0x0040004000400040ULL };
DECLARE_ALIGNED(8, const uint64_t, mask) = { 0x00ff00ff00ff00ffULL };
double ff_ph_40, mask;
uint64_t x0, x1, y0, y1, all;
double filter_x0, filter_x1, filter_y0, filter_y1;
const uint8_t *filter_x = bilinear_filters[x_offset];
const uint8_t *filter_y = bilinear_filters[y_offset];
x0 = (uint64_t)filter_x[0];
x1 = (uint64_t)filter_x[1];
y0 = (uint64_t)filter_y[0];
y1 = (uint64_t)filter_y[1];
all = x0 | x1 << 8 | y0 << 16 | y1 << 24;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
MMI_MTC1(%[all], %[ftmp14])
"punpcklbh %[ftmp14], %[ftmp14], %[ftmp0] \n\t"
"pshufh %[filter_x0], %[ftmp14], %[ftmp0] \n\t"
MMI_LI(%[tmp0], 0x10)
MMI_MTC1(%[tmp0], %[mask])
"ssrld %[ftmp14], %[ftmp14], %[mask] \n\t"
"pshufh %[filter_x1], %[ftmp14], %[ftmp0] \n\t"
"ssrld %[ftmp14], %[ftmp14], %[mask] \n\t"
"pshufh %[filter_y0], %[ftmp14], %[ftmp0] \n\t"
"ssrld %[ftmp14], %[ftmp14], %[mask] \n\t"
"pshufh %[filter_y1], %[ftmp14], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
MMI_LI(%[tmp0], 0x07)
MMI_MTC1(%[tmp0], %[ftmp14])
"pshufh %[filter_x0], %[filter_x0], %[ftmp0] \n\t"
"pshufh %[filter_x1], %[filter_x1], %[ftmp0] \n\t"
"pshufh %[filter_y0], %[filter_y0], %[ftmp0] \n\t"
"pshufh %[filter_y1], %[filter_y1], %[ftmp0] \n\t"
MMI_LI(%[tmp0], 0x0040004000400040)
MMI_MTC1(%[tmp0], %[ff_ph_40])
MMI_LI(%[tmp0], 0x00ff00ff00ff00ff)
MMI_MTC1(%[tmp0], %[mask])
// fdata3: fdata3[0] ~ fdata3[7]
VAR_FILTER_BLOCK2D_BIL_FIRST_PASS_8_A
@@ -1154,15 +1204,13 @@ static inline void var_filter_block2d_bil_8x(const uint8_t *src_ptr,
[ftmp11] "=&f"(ftmp[11]), [ftmp12] "=&f"(ftmp[12]),
[ftmp13] "=&f"(ftmp[13]), [ftmp14] "=&f"(ftmp[14]),
[tmp0] "=&r"(tmp[0]), [src_ptr] "+&r"(src_ptr), [temp2_ptr] "+&r"(temp2_ptr),
[counter]"+&r"(l_counter)
: [filter_x0] "f"((uint64_t)filter_x[0]),
[filter_x1] "f"((uint64_t)filter_x[1]),
[filter_y0] "f"((uint64_t)filter_y[0]),
[filter_y1] "f"((uint64_t)filter_y[1]),
[src_stride] "r"((mips_reg)src_stride), [ff_ph_40] "f"(ff_ph_40),
[mask] "f"(mask)
[counter]"+&r"(l_counter), [ff_ph_40] "=&f"(ff_ph_40), [mask] "=&f"(mask),
[filter_x0] "=&f"(filter_x0), [filter_x1] "=&f"(filter_x1),
[filter_y0] "=&f"(filter_y0), [filter_y1] "=&f"(filter_y1)
: [src_stride] "r"((mips_reg)src_stride), [all] "r"(all)
: "memory"
);
/* clang-format on */
}
#define SUBPIX_VAR8XN(H) \
@@ -1188,19 +1236,38 @@ static inline void var_filter_block2d_bil_4x(const uint8_t *src_ptr,
mips_reg l_counter = counter;
double ftmp[7];
mips_reg tmp[2];
DECLARE_ALIGNED(8, const uint64_t, ff_ph_40) = { 0x0040004000400040ULL };
DECLARE_ALIGNED(8, const uint64_t, mask) = { 0x00ff00ff00ff00ffULL };
double ff_ph_40, mask;
uint64_t x0, x1, y0, y1, all;
double filter_x0, filter_x1, filter_y0, filter_y1;
const uint8_t *filter_x = bilinear_filters[x_offset];
const uint8_t *filter_y = bilinear_filters[y_offset];
x0 = (uint64_t)filter_x[0];
x1 = (uint64_t)filter_x[1];
y0 = (uint64_t)filter_y[0];
y1 = (uint64_t)filter_y[1];
all = x0 | x1 << 8 | y0 << 16 | y1 << 24;
/* clang-format off */
__asm__ volatile (
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
MMI_MTC1(%[all], %[ftmp6])
"punpcklbh %[ftmp6], %[ftmp6], %[ftmp0] \n\t"
"pshufh %[filter_x0], %[ftmp6], %[ftmp0] \n\t"
MMI_LI(%[tmp0], 0x10)
MMI_MTC1(%[tmp0], %[mask])
"ssrld %[ftmp6], %[ftmp6], %[mask] \n\t"
"pshufh %[filter_x1], %[ftmp6], %[ftmp0] \n\t"
"ssrld %[ftmp6], %[ftmp6], %[mask] \n\t"
"pshufh %[filter_y0], %[ftmp6], %[ftmp0] \n\t"
"ssrld %[ftmp6], %[ftmp6], %[mask] \n\t"
"pshufh %[filter_y1], %[ftmp6], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
MMI_LI(%[tmp0], 0x07)
MMI_MTC1(%[tmp0], %[ftmp6])
"pshufh %[filter_x0], %[filter_x0], %[ftmp0] \n\t"
"pshufh %[filter_x1], %[filter_x1], %[ftmp0] \n\t"
"pshufh %[filter_y0], %[filter_y0], %[ftmp0] \n\t"
"pshufh %[filter_y1], %[filter_y1], %[ftmp0] \n\t"
MMI_LI(%[tmp0], 0x0040004000400040)
MMI_MTC1(%[tmp0], %[ff_ph_40])
MMI_LI(%[tmp0], 0x00ff00ff00ff00ff)
MMI_MTC1(%[tmp0], %[mask])
// fdata3: fdata3[0] ~ fdata3[3]
VAR_FILTER_BLOCK2D_BIL_FIRST_PASS_4_A
@@ -1232,15 +1299,14 @@ static inline void var_filter_block2d_bil_4x(const uint8_t *src_ptr,
: [ftmp0] "=&f"(ftmp[0]), [ftmp1] "=&f"(ftmp[1]), [ftmp2] "=&f"(ftmp[2]),
[ftmp3] "=&f"(ftmp[3]), [ftmp4] "=&f"(ftmp[4]), [ftmp5] "=&f"(ftmp[5]),
[ftmp6] "=&f"(ftmp[6]), [tmp0] "=&r"(tmp[0]), [src_ptr] "+&r"(src_ptr),
[temp2_ptr] "+&r"(temp2_ptr), [counter]"+&r"(l_counter)
: [filter_x0] "f"((uint64_t)filter_x[0]),
[filter_x1] "f"((uint64_t)filter_x[1]),
[filter_y0] "f"((uint64_t)filter_y[0]),
[filter_y1] "f"((uint64_t)filter_y[1]),
[src_stride] "r"((mips_reg)src_stride), [ff_ph_40] "f"(ff_ph_40),
[mask] "f"(mask)
[temp2_ptr] "+&r"(temp2_ptr), [counter]"+&r"(l_counter),
[ff_ph_40] "=&f"(ff_ph_40), [mask] "=&f"(mask),
[filter_x0] "=&f"(filter_x0), [filter_x1] "=&f"(filter_x1),
[filter_y0] "=&f"(filter_y0), [filter_y1] "=&f"(filter_y1)
: [src_stride] "r"((mips_reg)src_stride), [all] "r"(all)
: "memory"
);
/* clang-format on */
}
#define SUBPIX_VAR4XN(H) \
libs/libvpx/vpx_dsp/mips/vpx_convolve8_mmi.c
+5 -5
View File
@@ -105,7 +105,7 @@ static void convolve_horiz_mmi(const uint8_t *src, ptrdiff_t src_stride,
/* clang-format off */
__asm__ volatile(
"move %[tmp1], %[width] \n\t"
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"gsldlc1 %[filter1], 0x03(%[filter]) \n\t"
"gsldrc1 %[filter1], 0x00(%[filter]) \n\t"
"gsldlc1 %[filter2], 0x0b(%[filter]) \n\t"
@@ -178,7 +178,7 @@ static void convolve_vert_mmi(const uint8_t *src, ptrdiff_t src_stride,
(void)y_step_q4;
__asm__ volatile(
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"gsldlc1 %[ftmp4], 0x03(%[filter]) \n\t"
"gsldrc1 %[ftmp4], 0x00(%[filter]) \n\t"
"gsldlc1 %[ftmp5], 0x0b(%[filter]) \n\t"
@@ -271,7 +271,7 @@ static void convolve_avg_horiz_mmi(const uint8_t *src, ptrdiff_t src_stride,
__asm__ volatile(
"move %[tmp1], %[width] \n\t"
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"gsldlc1 %[filter1], 0x03(%[filter]) \n\t"
"gsldrc1 %[filter1], 0x00(%[filter]) \n\t"
"gsldlc1 %[filter2], 0x0b(%[filter]) \n\t"
@@ -354,7 +354,7 @@ static void convolve_avg_vert_mmi(const uint8_t *src, ptrdiff_t src_stride,
(void)y_step_q4;
__asm__ volatile(
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"gsldlc1 %[ftmp4], 0x03(%[filter]) \n\t"
"gsldrc1 %[ftmp4], 0x00(%[filter]) \n\t"
"gsldlc1 %[ftmp5], 0x0b(%[filter]) \n\t"
@@ -467,7 +467,7 @@ void vpx_convolve_avg_mmi(const uint8_t *src, ptrdiff_t src_stride,
__asm__ volatile(
"move %[tmp1], %[width] \n\t"
"xor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
"li %[tmp0], 0x10001 \n\t"
MMI_MTC1(%[tmp0], %[ftmp3])
"punpcklhw %[ftmp3], %[ftmp3], %[ftmp3] \n\t"