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bd3589a2fbb56486f3c76548a4197716ebcce8c7
You need an enabled jitter buffer for FEC to work. If a packet is missing we look in the jitter buffer for the next one, if the next packet is present we pass it to the decoder to extract the FEC info from it. If there's no FEC inside the packet, the Opus decoder will return PLC.
Merge pull request #262 in FS/freeswitch from feature/FS-7587-add-ipv6-support-to-verto-websockets to master
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Description
FreeSWITCH is a Software Defined Telecom Stack enabling the digital transformation from proprietary telecom switches to a versatile software implementation that runs on any commodity hardware. From a Raspberry PI to a multi-core server, FreeSWITCH can unlock the telecommunications potential of any device.
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